Vendor
Mobile phoneApple3nm node10W TDP
Apple A17 Pro (Apple)
First commercial 3nm smartphone chip with 6-core GPU featuring hardware Ray Tracing and a 35 TOPS Neural Engine.
Memory bandwidth1%
51.2 GB/s8 GB LPDDR5X
Peak compute / NPU1%
35 TOPS4.3 TF BF16
Transistor count9%
19.0 BDie size: 103.8 mm²
On-chip SRAM10%
24.8 MB24 MB SLC + 128 KB/core
Silicon die floorplan
60 FPS // 3D silicon package
Local LLM capability matrix
51.2 GB/s| Model | Parameters | Quantization | Memory | Estimated speed | Fit |
|---|
Operational profile
Architecture notes
| Foundry | TSMC 3nm |
| Packaging | TSMC InFO-PoP |
| Density | 183 MTr/mm² |
| Efficiency | 3.5 TOPS/W |
| Bus | 128-bit |
| Ridge point | 84 FLOPs/Byte |
Operational roofline
Compute-boundWorkload controls
Preset
Operational intensity64 FLOPs/B
Matrix dimension4096
Precision
Memory hierarchy and tile flow
Follow matrix tiles from off-chip memory through cache and SRAM into execution units.
1. Off-chip DRAM / HBM
8 GB LPDDR5X @ 51.2 GB/s
↓ Reload amplification: 1.4x
2. Shared L2 / system cache
24 MB shared SRAM
↓ High-bandwidth crossbar
3. On-chip SRAM
128 KB per core
↓ Register streaming
4. Tensor and compute engines
6 GPU cores + 16 NPU cores
Tile geometry
Tile M128
Tile N128
Tile K64
Pipeline stages2 (Double-Buffered)
SRAM required64 KB
Hardware limit128 KB
Utilization50%
Interactive systolic array
Watch tiles propagate through a 2D multiply-accumulate array.
| Chip model | Class | Process | TDP | Memory BW | VRAM | Peak BF16/FP16 | NPU TOPS | Llama-3 8B |
|---|
Custom silicon
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